Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips to base ceramic chip carriers, for example alumina carriers. The solder bump, typically a lead/tin (Pb/Sn) alloy such as 95 Pb/5 Sn alloy provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. This is described in U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application. Typically, malleable pads of metallic solder are formed on semiconductor chip contact sites and solder joinable sites are formed on conductors on the chip carrier. The chip carrier solder joinable sites are surrounded by non-solderable barriers so that when the solder on the semiconductor chip contact sites melts, to form a joint, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor chip suspended above the chip carrier.
Usually the circuit semiconductor chips are mounted on supporting substrates made of materials with coefficients of thermal expansion that differ from the coefficient of thermal expansion of the material of the semiconductor chip, i.e. silicon. Normally the semiconductor chips are formed of monocrystalline silicon with a coefficient of thermal expansion of about 2.5 parts per million (ppm.)/degree Celsius (° C.) and the substrate is formed of a ceramic material, typically alumina with a coefficient of thermal expansion of about 5.8 ppm./° C. In operation, the active and passive elements of each integrated semiconductor chip inevitably generate heat resulting in temperature fluctuations in both the chips and the supporting substrate since the heat is conducted through the solder joints. The chips and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of thermal expansion. This imposes stresses on the relatively rigid semiconductor chip solder joints.
The stress on the semiconductor chip solder joints during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual joint from the neutral or central point (DNP), and (3) the difference in the coefficients of thermal expansion of the material of the semiconductor chip and the substrate, and inversely proportional to the height of the solder joint, that is the spacing between the chip and the support substrate. The seriousness of the situation is further compounded by the fact that as the solder joints become smaller in diameter in order to accommodate the need for greater I/O density, the overall height decreases. U.S. Pat. No. 4,604,644 to Beckham, et al. and assigned to the assignee of the present application, describes a structure for electrically joining a semiconductor chip to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the chip and a corresponding solder wettable pad on the support substrate. Dielectric organic material is disposed between the peripheral area of the chip and the facing area of the substrate, the material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material. The preferred material disclosed in U.S. Pat. No. 4,604,644 is obtained from a polyimide resin available commercially and sold under the product name AI-10 by BP-Amoco Chemical Corporation, Chicago, Ill. AI-10 is formed by reacting a diamine such as p,p′ diaminodiphenylmethane with trimellitic anhydride or acylchloride of trimellitic anhydride. The polymer is further reacted with gamma. -amino propyl triethoxy silane or β-(3,4-epoxy cyclohexyl) ethyltrimethoxy silane. The coating material is described in IBM TDB September 1970 P. 825.
More recently, U.S. Pat. No. 5,668,904, and assigned to the assignee of the present application, describes a method of increasing the fatigue life of solder interconnections between a semiconductor chip and a supporting substrate. The method includes attaching the semiconductor chip to the substrate by a plurality of solder connections that extend from the supporting substrate to electrodes on the semiconductor chip to form a gap between the supporting substrate and the semiconductor chip. The gap is filled with a composition consisting of a cycloaliphatic polyepoxide and/or cyanate ester or prepolymers, and fillers such as aluminum nitride or aluminum oxide. The composition is then cured.
Although the above techniques have been quite successful in improving fatigue life of solder interconnections between a semiconductor chip and a supporting substrate, there still remains room for improvement in extending the fatigue life. An improved encapsulant composition for making an encapsulant has been developed to further improve fatigue life of solder interconnections between a semiconductor chip and a supporting substrate. It is believed that such a composition and the resultant electronic package will constitute a significant advancement in the art.